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PLDI 2021
Sun 20 - Sat 26 June 2021 Virtual Conference
Yatin Manerkar

Registered user since Mon 6 May 2019

Name: Yatin Manerkar

Bio: I am an incoming Assistant Professor in the Computer Science and Engineering (CSE) Department at the University of Michigan beginning Fall 2021. I recently completed my PhD in the Princeton Computer Science department, advised by Prof. Margaret Martonosi. I am currently doing a “pre-battical” with Prof. Sanjit Seshia at UC Berkeley in between graduation and starting at Michigan.

My research lies on the boundary between computer architecture and formal methods, and focuses on developing automated formal methodologies and tools for the design and verification of computing systems. My work spans the hardware/software stack, from high-level programming languages down to low-level Verilog circuits. During my PhD, my research focused on the verification of memory consistency model (MCM) properties in parallel hardware and software. MCMs specify the ordering rules for memory operations used for communication and synchronization in shared-memory parallel programs, so MCM verification is critical to parallel system correctness. My work has found real-world bugs in C++ compilers, an open-source processor implementation in Verilog, and in the widely-used RISC-V instruction set (ISA). My work has also enriched the formal methods community by developing new formal analysis techniques.

Before joining Princeton, I completed my BASc in Computer Engineering at the University of Waterloo and a M.S. in Computer Science and Engineering at the University of Michigan. I also worked full-time at Qualcomm Research for one year.

Country: United States

Affiliation: UC Berkeley, University of Michigan

Personal website: https://www.cs.princeton.edu/~manerkar/

Research interests: Formal verification, memory consistency models, cache coherence, computer architecture

Contributions

PLDI 2021 Committee Member in Student Research Competition (SRC) within the SRC-track
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