Non-volatile memory (NVM) is a cutting-edge storage technology that promises the performance of DRAM with the durability of SSD.
Recent work has proposed several \emph{persistency models} for mainstream architectures such as Intel-x86 and Armv8, describing the order in which writes are propagated to NVM.
However, these models have several limitations; most notably, they either lack operational models or do not support persistent synchronization patterns.

We close this gap by revamping the existing persistency models.
First, inspired by the recent work on promising semantics, we propose a \emph{unified operational style} for describing persistency using \emph{views}, and develop view-based operational persistency models for Intel-x86 and Armv8, thus presenting the \emph{first} operational model for Armv8 persistency.
Next, we propose a \emph{unified axiomatic style} for describing hardware persistency, allowing us to recast and repair the existing axiomatic models of Intel-x86 and Armv8 persistency.
We prove that our axiomatic models are equivalent to the authoritative semantics reviewed by Intel and Arm engineers.
We further prove that each axiomatic hardware persistency model is equivalent to its operational counterpart.
Finally, we develop a persistent model checking algorithm and tool, and use it to verify several representative examples.